Digital Design by M.Morris Mano 3rd edition

Digital Design by M.Morris Mano 3rd edition

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Contents:

• Nine sections on Verilog Hardware Description Language (HDL) inserted in discrete sections, allowing the material to be covered or skipped as desired. The Verilog HDL presentation is at a suitable level for beginning students who are learning digital circuits for the first time.
• Reorganized material on combinational circuits is now covered in a single chapter.
• The emphasis in the sequential circuits chapters is now on design with D flip-flops instead of JK and SR flip-flops.
• The material on memory and programmable logic are now consolidated in one chapter.
• Chapter 8 consists mostly of new material and now covers digital design in the Register Transfer Level (P) FL), preparing the reader for more advanced design projects and further Verilog HDL studies.
• A new section in Chapter 11 supplements the laboratory experiments with HDL experiments. These enable the reader to check the circuits designed in the laboratory by means of hardware components and/or by HDL simulation.
• Text accompanied by Verilog simulator software―SynaptiCAD's VeriLogger Pro evaluation version, a Verilog simulation environment that combines all of the features of a traditional Verilog simulator with a powerful graphical test vector generator. Fast model testing in VeriLogger Pro allows the reader to perform bottom-up testing of every model in design. All of the HDL examples in the book can be found on the CD-ROM.

Digital Communications By J.S.Chitode

Digital Communications (1-3 Units Only) By J.S.Chitode... 

 

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Digital Communications Fundamentals and Applications by Bernard Sklar

Digital Communications Fundamentals and Applications by Bernard Sklar

 

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Contents

PREFACE
1 SIGNALS AND SPECTRA                                                                                
1.1 Digital Communication Signal Processing,                                                    
1.1.1 Why Digital?,                                                                                                
1.1.2 Typical Block Diagram and Transformations,
1.1.3 Basic Digital Communication Nomenclature,
1.1.4 Digital versus Analog Performance Criteria,
1.2 Classification of Signals,
1.2.1 Deterministic and Random Signals,
1.2.2 Periodic and Nonperiodic Signals,
1.2.3 Analog and Discrete Signals,
1.2.4 Energy and Power Signals,
1.2.5 The Unit Impulse Function,
1.3 Spectral Density,
1.3.1 Energy Spectral Density,
1.3.2 Power Spectral Density,
1.4 Autocorrelation,
1.4.1 Autocorrelation of an Energy Signal,
1.4.2 Autocorrelation of a Periodic (Power) Signal,
1.5 Random Signals,
1.5.1 Random Variables,
1.5.2 Random Processes,
1.5.3 Time Averaging and Ergodicity,
1.5.4 Power Spectral Density of a Random Process,
1.5.5 Noise in Communication Systems,
1.6 Signal Transmission through Linear Systems,
1.6.1 Impulse Response,
1.6.2 Frequency Transfer Function,
1.6.3 Distortionless Transmission,
1.6.4 Signals, Circuits, and Spectra,
1.7 Bandwidth of Digital Data,
1.7.1 Baseband versus Bandpass,
1.7.2 The Bandwidth Dilemma,
1.8 Conclusion,
2 FORMATTING AND BASEBAND MODULATION
2.1 Baseband Systems,
2.2 Formatting Textual Data (Character Coding),
2.3 Messages, Characters, and Symbols,
2.3.7 Example of Messages, Characters, and Symbols,
2.4 Formatting Analog Information,
2.4.1 The Sampling Theorem,
2.4.2 Aliasing,
2.4.3 Why Oversample?
2.4.4 Signal Interface for a Digital System,
2.5 Sources of Corruption,
2.5.7 Sampling and Quantizing Effects,
2.5.2 Channel Effects,
2.5.3 Signal-to-Noise Ratio for Quantized Pulses,
2.6 Pulse Code Modulation,
2.7 Uniform and Nonuniform Quantization,
2.7.7 Statistics of Speech Amplitudes,
2.7.2 Nonuniform Quantization,
2.7.3 Companding Characteristics,
2.8 Baseband Modulation,
2.8.1 Waveform Representation of Binary Digits,
2.8.2 PCM Waveform Types,
2.8.3 Spectral Attributes of PCM Waveforms,
2.8.4 Bits per PCM Word and Bits per Symbol,
2.8.5 M-ary Pulse Modulation Waveforms,
2.9 Correlative Coding,
2.9.7 Duobinary Signaling,
2.9.2 Duobinary Decoding,
2.9.3 Preceding,
2.9.4 Duobinary Equivalent Transfer Function,
2.9.5 Comparison of Binary with Duobinary Signaling,
2.9.6 Poly binary Signaling,
2.10 Conclusion,
3 BASED AND DEMODULATION/DETECTION
3.1 Signals and Noise,
3.1.1 Error-Performance Degradation in Communication Systems,
3.1.2 Demodulation and Detection,
3.1.3 A Vectorial View of Signals and Noise,
3.1.4 The Basic SNR Parameter for Digital Communication Systems,
3.1.5 Why Eb/N0 Is a Natural Figure of Merit,
3.2 Detection of Binary Signals in Gaussian Noise,
3.2.1 Maximum Likelihood Receiver Structure,
3.2.2 The Matched Filter,
3.2.3 Correlation Realization of the Matched Filter,
3.2.4 Optimizing Error Performance,
3.2.5 Error Probability Performance of Binary Signaling,
3.3 Intersymbol Interference,
3.3.1 Pulse Shaping to Reduce ISI,
3.3.2 Two Types of Error-Performance Degradation,
3.3.3 Demodulation/Detection of Shaped Pulses,
3.4 Equalization,
3.4.1 Channel Characterization,
3.4.2 Eye Pattern
3.4.3 Equalizer Filter Types,
3.4.4 Preset and Adaptive Equalization,
3.4.5 Filter Update Rate,
3.5 Conclusion,
4 BANDPASS MODULATION AND DEMODULATION/DETECTION
4.1 Why Modulate?
4.2 Digital Bandpass Modulation Techniques,
4.2.1 Phasor Representation of a Sinusoid,
4.2.2 Phase Shift Keying,
4.2.3 Frequency Shift Keying,
4.2.4 Amplitude Shift Keying,
4.2.5 Amplitude Phase Keying,
4.2.6 Waveform Amplitude Coefficient,
4.3 Detection of Signals in Gaussian Noise,
4.3.1 Decision Regions,
4.3.2 Correlation Receiver,
4.4 Coherent Detection,
4.4.1 Coherent Detection of PSK,
4.4.2 Sampled Matched Filter,
4.4.3 Coherent Detection of Multiple Phase Shift Keying,
4.4.4 Coherent Detection of FSK,
4.5 Noncoherent Detection,
4.5.1 Detection of Differential PSK,
4.5.2 Binary Differential PSK Example,
4.5.3 Noncoherent Detection of FSK,
4.5.4 Required Tone Spacing for Noncoherent Orthogonal FSK,
4.6 Complex Envelope,
4.6.1 Quadrature Implementation of a Modulator,
4.6.2 D8PSK Modulator Example,
4.6.3 D8PSK Demodulator Example,
4.7 Error Performance for Binary Systems,
4.7.1 Probability of Bit Error for Coherently Detected BPSK,
4.7.2 Probability of Bit Error for Coherently Detected
Differentially Encoded Binary PSK,
4.7.3 Probability of Bit Error for Coherently Detected
Binary Orthogonal FSK,
4.7.4 Probability of Bit Error for Noncoherently Detected
Binary Orthogonal FSK,
4.7.5 Probability of Bit Error for Binary DPSK,
4.7.6 Comparison of Bit Error Performance for Various
Modulation Types,
4.8 M-ary Signaling and Performance,
4.8.1 Ideal Probability of Bit Error Performance,
4.8.2 M-ary Signaling,
4.8.3 Vectorial View of MPSK Signaling,
4.8.4 BPSK and QPSK Have the Same Bit Error Probability,
4.8.5 Vectorial View of MFSK Signaling,
4.9 Symbol Error Performance for M-ary Systems (M > 2),
4.9.1 Probability of Symbol Error for MPSK,
4.9.2 Probability of Symbol Error for MFSK,
4.9.3 Bit Error Probability versus Symbol Error Probability
for Orthogonal Signals,
4.9.4 Bit Error Probability versus Symbol Error Probability
for Multiple Phase Signaling,
4.9.5 Effects of Intersymbol Interference,
4.10 Conclusion,
5 COMMUNICATIONS LINK ANALYSIS 
5.1 What the System Link Budget Tells the System Engineer,
5.2 The Channel,
5.2.7 The Concept of Free Space,
5.2.2 Error-Performance Degradation,
5.2.3 Sources of Signal Loss and Noise,
5.3 Received Signal Power and Noise Power,
5.3J The Range Equation,
5.3.2 Received Signal Power as a Function of Frequency,
5.3.3 Path Loss is Frequency Dependent,
5.3.4 Thermal Noise Power,
5.4 Link Budget Analysis,
5.4.1 Two E//NQ Values of Interest,
5.4.2 Link Budgets are Typically Calculated in Decibels,
5.4.3 How Much Link Margin is Enough?
5.4.4 Link Availability,
5.5 Noise Figure, Noise Temperature, and System Temperature,
5.5 J Noise Figure,
5.5.2 Noise Temperature,
5.5.3 Line Loss,
5.5.4 Composite Noise Figure and Composite Noise Temperature,
5.5.5 System Effective Temperature,
5.5.6 Sky Noise Temperature,
5.6 Sample Link Analysis,
5.6.1 Link Budget Details,
5.6.2 Receiver Figure of Merit,
5.6.3 Received Isotropic Power,
5.7 Satellite Repeaters,
5.7.7 Nonregenerative Repeaters,
5.7.2 Nonlinear Repeater Amplifiers,
5.8 System Trade-Offs,
5.9 Conclusion,
6 CHANNEL CODING: PART 1 
6.1 Waveform Coding and Structured Sequences,
6.1.1 Antipodal and Orthogonal Signals,
6.1.2 M-ary Signaling,
6.1.3 Waveform Coding,
6.1.4 Waveform-Coding System Example,
6.2 Types of Error Control,
6.2.1 Terminal Connectivity,
6.2.2 Automatic Repeat Request,
6.3 Structured Sequences,
6.3.1 Channel Models,
6.3.2 Code Rate and Redundancy,
6.3.3 Parity Check Codes,
6.3.4 Why Use Error-Correction Coding?
6.4 Linear Block Codes,
6.4.1 Vector Spaces,
6.4.2 Vector Subspaces,
6.4.3 A (6, 3) Linear Block Code Example,
6.4.4 Generator Matrix,
6.4.5 Systematic Linear Block Codes,
6.4.6 Parity-Check Matrix,
6.4.7 Syndrome Testing,
6.4.8 Error Correction,
6.4.9 Decoder Implementation,
6.5 Error-Detecting and Correcting Capability,
6.5.1 Weight and Distance of Binary Vectors,
6.5.2 Minimum Distance of a Linear Code,
6.5.3 Error Detection and Correction,
6.5.4 Visualization of a 6-Tuple Space,
6.5.5 Erasure Correction,
6.6 Usefulness of the Standard Array,
6.6.1 Estimating Code Capability,
6.6.2 An (n, k) Example,
6.6.3 Designing the (8, 2) Code,
6.6.4 Error Detection versus Error Correction Trade-Offs,
6.6.5 The Standard Array Provides Insight,
6.7 Cyclic Codes,
6.7.7 Algebraic Structure of Cyclic Codes,
6.7.2 Binary Cyclic Code Properties,
6.7.3 Encoding in Systematic Form,
6.7.4 Circuit for Dividing Polynomials,
6.7.5 Systematic Encoding with an (n - k)-Stage Shift Register,
6.7.6 Error Detection with an (n - k)-Stage Shift Register,
6.8 Weil-Known Block Codes,
6.8.1 Hamming Codes,
6.8.2 Extended Golay Code,
6.8.3 BCH Codes,
6.9 Conclusion,
7 CHANNEL CODING: PART 2 
7.1 Convolutional Encoding,
7.2 Convolutional Encoder Representation,
7.2.1 Connection Representation,
7.2.2 State Representation and the State Diagram,
7.2.3 The Tree Diagram,
7.2.4 The Trellis Diagram,
7.3 Formulation of the Convolutional Decoding Problem,
7.3.1 Maximum Likelihood Decoding,
7.3.2 Channel Models: Hard versus Soft Decisions,
7.3.3 The Viterbi Convolutional Decoding Algorithm,
7.3.4 An Example of Viterbi Convolutional Decoding,
7.3.5 Decoder Implementation,
7.3.6 Path Memory and Synchronization,
7.4 Properties of Convolutional Codes,
7.4.1 Distance Properties of Convolutional Codes,
7.4.2 Systematic and Nonsystematic Convolutional Codes,
7.4.3 Catastrophic Error Propagation in Convolutional Codes,
7.4.4 Performance Bounds for Convolutional Codes,
7.4.5 Coding Gain,
7.4.6 Best Known Convolutional Codes,
7.4.7 Convolutional Code Rate Trade-Off,
7.4.8 Soft-Decision Viterbi Decoding,
7.5 Other Convolutional Decoding Algorithms,
7.5.1 Sequential Decoding,
7.5.2 Comparisons and Limitations of Viterbi and Sequential Decoding,
7.5.3 Feedback Decoding,
7.6 Conclusion,
8 CHANNEL CODING: PART 3 
8.1 Reed-Solomon Codes,
8.1.1 Reed-Solomon Error Probability,
8.1.2 Why R-S Codes Perform Well Against Burst Noise,
8.1.3 R-S Performance as a Function of Size,
Redundancy, and Code Rate,
8.1.4 Finite Fields
8.1.5 Reed-Solomon Encoding,
8.1.6 Reed-Solomon Decoding,
8.2 Interleaving and Concatenated Codes,
8.2.1 Block Interleaving,
8.2.2 Convolutional Interleaving,
8.2.3 Concatenated Codes,
8.3 Coding and Interleaving Applied to the Compact Disc
Digital Audio System,
8.3.1 CIRC Encoding,
8.3.2 CIRC Decoding,
8.3.3 Interpolation and Muting,
8.4 Turbo Codes,
8.4.1 Turbo Code Concepts,
8.4.2 Log-Likelihood Algebra,
8.4.3 Product Code Example,
8.4.4 Encoding with Recursive Systematic Codes,
8.4.5 A Feedback Decoder,
8.4.6 The MAP Decoding Algorithm,
8.4.7 MAP Decoding Example,
8.5 Conclusion,
Appendix 8A The Sum of Log-Likelihood Ratios,
9 MODULATION AND CODING TRADE-OFFS 
9.1 Goals of the Communications System Designer,
9.2 Error Probability Plane,
9.3 Nyquist Minimum Bandwidth,
9.4 Shannon-Hartley Capacity Theorem,
9.4.1 Shannon Limit,
9.4.2 Entropy,
9.4.3 Equivocation and Effective Transmission Rate,
9.5 Bandwidth Efficiency Plane,
9.5.7 Bandwidth Efficiency ofMPSK and MFSK Modulation,
9.5.2 Analogies Between Bandwidth-Efficiency
and Error Probability Planes,
9.6 Modulation and Coding Trade-Offs,
9.7 Defining, Designing, and Evaluating Digital
Communication Systems,
9.7.7 M-ary Signaling,
9.7.2 Bandwidth-Limited Systems,
9.7.3 Power-Limited Systems,
9.7.4 Requirements for MPSK and MFSK Signaling,
9.7.5 Bandwidth-Limited Uncoded System Example,
9.7.6 Power-Limited Uncoded System Example,
9.7.7 Bandwidth-Limited and Power-Limited
Coded System Example,
9.8 Bandwidth-Efficient Modulation,
9.5.7 QPSK and Offset QPSK Signaling,
9.8.2 Minimum Shift Keying,
9.8.3 Quadrature Amplitude Modulation,
9.9 Modulation and Coding for Bandlimited Channels,
9.9.7 Commercial Telephone Modems,
9.9.2 Signal Constellation Boundaries
9.9.3 Higher Dimensional Signal Constellations,
9.9.4 Higher-Density Lattice Structures,
9.9.5 Combined Gain: N-Sphere Mapping and Dense Lattice,
9.10 Trellis-Coded Modulation,
9.70.7 The Idea Behind Trellis-Coded Modulation (TCM),
9.10.2 TCM Encoding,
9.10.3 TCM Decoding,
9.10.4 Other Trellis Codes,
9.10.5 Trellis-Coded Modulation Example,
9.10.6 Multi-Dimensional Trellis-Coded Modulation,
9.11 Conclusion,
10 SYNCHRONIZATION 
10.1 Introduction,
10.1.1 Synchronization Defined,
10.1.2 Costs versus Benefits,
10.1.3 Approach and Assumptions,
10.2 Receiver Synchronization,
10.2.1 Frequency and Phase Synchronization,
10.2.2 Symbol Synchronization—Discrete Symbol Modulations,
10.2.3 Synchronization with Continuous-Phase Modulations (CPM),
10.2.4 Frame Synchronization,
10.3 Network Synchronization,
10.3.1 Open-Loop Transmitter Synchronization,
10.3.2 Closed-Loop Transmitter Synchronization,
10.4 Conclusion,
11 MULTIPLEXING AND MULTIPLE ACCESS
11.1 Allocation of the Communications Resource,
11.1.1 Frequency-Division Multiplexing/Multiple Access,
11.1.2 Time-Division Multiplexing/Multiple Access,
11.1.3 Communications Resource Channelization,
11.1.4 Performance Comparison ofFDMA and TDMA,
11.1.5 Code-Division Multiple Access,
11.1.6 Space-Division and Polarization-Division Multiple Access,
11.2 Multiple Access Communications System and Architecture,
11.2.1 Multiple Access Information Flow,
11.2.2 Demand Assignment Multiple Access,
11.3 Access Algorithms,
11.3.1 ALOHA
11.3.2 Slotted ALOHA,
11.3.3 Reservation-ALOHA,
11.3.4 Performance Comparison ofS-ALOHA and R-ALOHA,
11.3.5 Polling Techniques,
11.4 Multiple Access Techniques Employed with INTELSAT,
11.4.1 Preassigned FDM/FM/FDMA or MCPC Operation,
11.4.2 MCPC Modes of Accessing an INTELSA T Satellite,
11.4.3 SPADE Operation,
11.4.4 TDMA in INTELSAT,
11.4.5 Satellite-Switched TDMA in INTELSAT,
11.5 Multiple Access Techniques for Local Area Networks,
11.5.1 Carrier-Sense Multiple Access Networks,
11.5.2 Token-Ring Networks,
11.5.3 Performance Comparison of CSMA/CD and Token-Ring Networks,
11.6 Conclusion,
12 SPREAD-SPECTRUM TECHNIQUES 
12.1 Spread-Spectrum Overview,
12.1.1 The Beneficial Attributes of Spread-Spectrum Systems,
12.1.2 A Catalog of Spreading Techniques,
12.1.3 Model for Direct-Sequence Spread-Spectrum
Interference Rejection,
12.1.4 Historical Background,
12.2 Pseudonoise Sequences,
72.2.1 Randomness Properties,
12.2.2 Shift Register Sequences,
12.2.3 PN Autocorrelation Function,
12.3 Direct-Sequence Spread-Spectrum Systems,
12.3.1 Example of Direct Sequencing,
12.3.2 Processing Gain and Performance,
12.4 Frequency Hopping Systems,
12.4.1 Frequency Hopping Example,
12.4.2 Robustness,
12.4.3 Frequency Hopping with Diversity,
12.4.4 Fast Hopping versus Slow Hopping,
12.4.5 FFH/MFSK Demodulator,
12.4.6 Processing Gain,
12.5 Synchronization,
12.5.1 Acquisition,
12.5.2 Tracking,
12.6 Jamming Considerations,
12.6.1 The Jamming Game,
12.6.2 Broadband Noise Jamming,
12.6.3 ^Partial-Band Noise Jamming,
12.6.4 . Multiple-Tone Jamming,
12.6.5 Pulse Jamming,
12.6.6 Repeat-Back Jamming,
12.6.7 BLADES System,
12.7 Commercial Applications,
12.7.1 Code-Division Multiple Access,
12.7.2 Multipath Channels,
12.7.3 The FCC Part 15 Rules for Spread-Spectrum Systems,
12.7.4 Direct Sequence versus Frequency Hopping,
12.8 Cellular Systems,
12.8.1 Direct Sequence CDMA,
12.8.2 Analog FM versus TDMA versus CDMA,
12.8.3 Interference-Limited versus Dimension-Limited Systems,
12.8.4 IS-95 CDMA Digital Cellular System,
12.9 Conclusion,
13 SOURCE CODING 
13.1 Sources,
13.1.1 Discrete Sources,
13.1.2 Waveform Sources,
13.2 Amplitude Quantizing,
13.2.1 Quantizing Noise,
13.2.2 Uniform Quantizing,
13.2.3 Saturation,
13.2.4 Dithering,
13.2.5 Nonuniform Quantizing,
13.3 Differential Pulse-Code Modulation,
13.3.1 One-Tap Prediction,
13.3.2 N-Tap Prediction,
13.3.3 Delta Modulation,
13.3.4 Sigma-Delta Modulation,
13.3.5 Sigma-Delta A-to-D Converter (ADC),
13.3.6 Sigma-Delta D-to-A Converter (DAC),
13.4 Adaptive Prediction,
13.4.1 Forward Prediction,
13.4.2 Synthesis/Analysis Coding,
13.5 Block Coding,
13.5.1 Vector Quantizing,
13.6 Transform Coding,
13.6.1 Quantization for Transform Coding,
13.6.2 Subband Coding,
13.7 Source Coding for Digital Data,
13.7.1 Properties of Codes,
13.7.2 Huffman Codes,
13.7.3 Run-Length Codes,
13.8 Examples of Source Coding,
13.8.1 Audio Compression,
13.8.2 Image Compression,
13.9 Conclusion,
14 ENCRYPTION AND DECRYPTION 
14.1 Models, Goals, and Early Cipher Systems,
14.1.1 A Model of the Encryption and Decryption Process,
14.1.2 System Goals,
14.1.3 Classic Threats,
14.1.4 Classic Ciphers,
14.2 The Secrecy of a Cipher System,
14.2.1 Perfect Secrecy,
14.2.2 Entropy and Equivocation,
14.2.3 Rate of a Language and Redundancy,
14.2.4 Unicity Distance and Ideal Secrecy,
14.3 Practical Security,
14.3.1 Confusion and Diffusion,
14.3.2 Substitution,
14.3.3 Permutation,
14.3.4 Product Cipher Systems,
14.3.5 The Data Encryption Standard,
14.4 Stream Encryption,
14.4.1 Example of Key Generation Using a Linear
Feedback Shift Register,
14.4.2 Vulnerabilities of Linear Feedback Shift Registers,
14.4.3 Synchronous and Self-Synchronous Stream
Encryption Systems,
14.5 Public Key Cryptosystems,
14.5.1 Signature Authentication using a Public Key Cryptosystem,
14.5.2 A Trapdoor One-Way Function,
14.5.3 The Rivest-Shamir-Adelman Scheme,
14.5.4 The Knapsack Problem,
14.5.5 A Public Key Cryptosystem based on a Trapdoor Knapsack,
14.6 Pretty Good Privacy,
14.6.1 Triple-DBS, CAST, and IDEA,
14.6.2 Diffie-Hellman (Elgamal Variation) and RSA,
14.6.3 PGP Message Encryption,
14.6.4 PGP Authentication and Signature,
14.7 Conclusion,
15 FADING CHANNELS 
15.1 The Challenge of Communicating over Fading Channels,
15.2 Characterizing Mobile-Radio Propagation,
75.2.7 Large-Scale Fading,
15.2.2 Small-Scale Fading,
15.3 Signal Time-Spreading,
75.3.7 Signal Time-Spreading Viewed in the Time-Delay Domain,
15.3.2 Signal Time-Spreading Viewed in the Frequency Domain,
15.3.3 Examples of Flat Fading and Frequency-Selective Fading,
15.4 Time Variance of the Channel Caused by Motion,
75.4.7 Time Variance Viewed in the Time Domain,
15.4.2 Time Variance Viewed in the Doppler-Shift Domain,
15.4.3 Performance over a Slow-and Flat-Fading Rayleigh Channel,
15.5 Mitigating the Degradation Effects of Fading,
75.5.7 Mitigation to Combat Frequency-Selective Distortion,
75.5.2 Mitigation to Combat Fast-Fading Distortion,
15.5.3 Mitigation to Combat Loss in SNR,
15.5.4 Diversity Techniques,
15.5.5 Modulation Types for Fading Channels,
15.5.6 The Role of an Interleaver,
15.6 Summary of the Key Parameters Characterizing Fading Channels,
75.6.7 Fast Fading Distortion: Case 1,
15.6.2 Frequency-Selective Fading Distortion: Case 2,
15.6.3 Fast-Fading and Frequency-Selective Fading Distortion: Case 3,
15.7 Applications: Mitigating the Effects of Frequency-Selective Fading,
75.7.7 The Viterbi Equalizer as Applied to GSM,
15.7.2 The Rake Receiver as Applied to Direct-Sequence
Spread-Spectrum (DS/SS) Systems,
15.8 Conclusion,
A A REVIEW OF FOURIER TECHNIQUES
A.I Signals, Spectra, and Linear Systems,
A.2 Fourier Techniques for Linear System Analysis,
A2.7 Fourier Series Transform,
A.2.2 Spectrum of a Pulse Train,
A.2.3 Fourier Integral Transform,
A.3 Fourier Transform Properties,
A.3.1 Time Shifting Property,
A.3.2 Frequency Shifting Property,
A.4 Useful Functions,
A.4.1 Unit Impulse Function,
A.4.2 Spectrum of a Sinusoid
A.5 Convolution,
A5.7 Graphical Example of Convolution,
A.5.2 Time Convolution Property,
A.5.3 Frequency Convolution Property,
A.5.4 Convolution of a Function with a Unit Impulse,
A.5.5 Demodulation Application of Convolution,
A.6 Tables of Fourier Transforms and Operations,
B FUNDAMENTALS OF STATISTICAL DECISION THEORY 
B.I Bayes' Theorem,
5.7.7 Discrete Form of Bayes'Theorem,
B.1.2 Mixed Form of Bayes'Theorem,
B.2 Decision Theory,
5.2.7 Components of the Decision Theory Problem,
B.2.2 The Likelihood Ratio Test and the Maximum
A Posteriori Criterion,
B.2.3 The Maximum Likelihood Criterion,
B.3 Signal Detection Example,
B.3.1 The Maximum Likelihood Binary Decision,
B.3.2 Probability of Bit Error,
C RESPONSE OF A CORRELATOR TO WHITE NOISE 
D OFTEN-USED IDENTITIES 
E s-DOMAIN, z-DOMAIN AND DIGITAL FILTERING 
E.I The Laplace Transform,
£.7.7 Standard Laplace Transforms,
E.1.2 Laplace Transform Properties,
E.1.3 Using the Laplace Transform,
E.1.4 Transfer Function,
E.1.5 RC Circuit Low Pass Filtering,
E.1.6 Poles and Zeroes,
E.1.7 Linear System Stability,
E.2 The z-Transform,
E.2.1 Calculating the z-Transform,
E.2.2 The Inverse z-Transform,
E.3 Digital Filtering,
E.3.1 Digital Filter Transfer Function,
E.3.2 Single Pole Filter Stability,
E.3.3 General Digital Filter Stability,
E.3.4 z-Plane Pole-Zero Diagram and the Unit Circle,
£.3.5 Discrete Fourier Transform of Digital Filter Impulse Response,
E.4 Finite Impulse Response Filter Design,
E.4.1 FIR Filter Design,
E.4.2 The FIR Differentiator,
E.5 Infinite Impulse Response Filter Design,
E.5.1 Backward Difference Operator,
£.5.2 HR Filter Design using the Bilinear Transform,
E.5.3 The IIR Integrator,
F LIST OF SYMBOLS
INDEX

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Chapter 1 - Basic Electronics 1
1.0 The Atom 1
1.1 Isotopes and Ions 2
1.2 Static Electricity 3
1.3 Electrical Charge 4
1.3.1 Voltage 4
1.3.2 Current 4
1.3.3 Power 5
1.3.4 Ohm's Law 5
1.4 Electrical Circuits 6
1.4.1 Types of Circuits 6
1.5 Circuit Elements 8
1.5.1 Resistors 9
1.5.2 Revisiting Ohm's Law 9
1.5.3 Resistors in Series and Parallel 10
1.5.4 Capacitors 12
1.5.5 Capacitors in Series and in Parallel 13
1.5.6 Inductors 14
1.5.7 Transformers 15
1.6 Semiconductors 15
1.6.1 Integrated Circuits 16
1.6.2 Semiconductor Electronics 16
1.6.3 P-Type and N-Type Silicon 17
1.6.4 The Diode 17
Chapter 2 - Number Systems 19
2.0 Counting 19
2.0.1 The Tally System 19
2.0.2 Roman Numerals 20
2.1 The Origins of the Decimal System 20
2.1.1 Number Systems for Digital-Electronics 22
2.1.2 Positional Characteristics 22
2.1.3 Radix or Base of a Number System 23
v
2.2 Types of Numbers 23
2.2.1 Whole Numbers 24
2.2.2 Signed Numbers 24
2.2.3 Rational, Irrational, and Imaginary Numbers 24
2.3 Radix Representations 25
2.3.1 Decimal versus Binary Numbers 25
2.3.2 Hexadecimal and Octal 26
2.4 Number System Conversions 27
2.4.1 Binary-to-ASCII-Decimal 28
2.4.2 Binary-to-Hexadecimal Conversion 29
2.4.3 Decimal-to-Binary Conversion 29
Chapter 3 - Data Types and Data Storage 33
3.0 Electronic-Digital Machines 33
3.1 Character Representations 33
3.1.1 ASCII 34
3.1.2 EBCDIC and IBM 36
3.1.3 Unicode 36
3.2 Storage and Encoding of Integers 37
3.2.1 Signed and Unsigned Representations 37
3.2.2 Word Size 38
3.2.3 Byte Ordering 39
3.2.4 Sign-Magnitude Representation 40
3.2.5 Radix Complement Representation 41
3.3 Encoding of Fractional Numbers 44
3.3.1 Fixed-Point Representations 45
3.3.2 Floating-Point Representations 46
3.3.3 Standardized Floating-Point Representations 47
3.3.4 IEEE 754 Single Format 48
3.3.5 Encoding and Decoding Floating-Point Numbers 50
3.4 Binary-Coded Decimals (BCD) 51
3.4.1 Floating-Point BCD 52
Chapter 4 - Digital Logic, Arithmetic, and Conversions 55
4.0 Microcontroller Logic and Arithmetic 55
4.0.1 CPU Flags 55
4.0.2 Word Size 56
4.1 Logical Instructions 56
4.1.1 Logical AND 57
4.1.2 Logical OR 57
4.1.3 Logical XOR 57
4.1.4 Logical NOT 58
4.2 Microcontroller Arithmetic 58
4.2.1 Unsigned and Two’s Complement Arithmetic 58
4.2.2 Operations on Decimal Numbers 60
4.3 Bit Manipulations and Auxiliary Operations 62
4.3.1 Bit Shift and Rotate 62
4.3.2 Comparison Operations 63
4.3.3 Other Support Operations 63
vi Microcontroller Programming
4.4 Unsigned Binary Arithmetic 64
4.4.1 Multi-byte Unsigned Addition 64
4.4.2 Unsigned Multiplication 65
4.4.3 Unsigned Division 67
4.5 Signed Binary Arithmetic 67
4.5.1 Overflow Detection in Signed Arithmetic 69
4.5.2 Sign Extension Operations 70
4.5.3 Multi-byte Signed Operations 71
4.6 Data Format Conversions 72
4.6.1 BCD Digits to ASCII Decimal 72
4.6.2 Unsigned Binary to ASCII Decimal Digits 73
4.6.3 ASCII Decimal String to Unsigned Binary 73
4.6.4 Unsigned Binary to ASCII Hexadecimal Digits 75
4.6.6 Signed Numerical Conversions 76
Chapter 5 - Circuits and Logic Gates 77
5.0 Digital Circuits 77
5.1 The Diode Revisited 78
5.1.1 The Light-Emitting Diode (LED) 79
5.2 The Transistor 81
5.2.1 Bipolar Transistor 81
5.2.2 MOS Transistor 83
5.3 Logic Gates 84
5.4 Transistor-Transistor Logic 85
5.4.1 Inverter Gates 86
5.4.2 The AND Gate 87
5.4.3 The NAND Gate 87
5.4.4 The OR Gate 88
5.4.5 The NOR Gate 88
5.4.6 Positive and Negative Logic 89
5.4.7 The XOR Gate 90
5.4.8 Schmitt Trigger Inverter 91
5.5 Other TTL Logic Families 93
5.6 CMOS Logic Gates 93
Chapter 6 - Circuit Components 95
6.0 Power Supplies 95
6.1 Clocked Logic and Flip-flops 96
6.1.1 The RS Flip-flop 96
6.1.2 Clocked RS Flip-flop 98
6.1.3 The D Flip-flop 99
6.1.4 The Edge-triggered D Flip-flop 100
6.1.5 Preset and Clear Signals 101
6.1.6 D Flip-flop Waveform Action 102
6.1.7 Flip-flop Applications 103
6.2 Clocks 103
6.2.1 Clock Waveforms 104
6.2.2 The TTL Clock 105
6.2.3 The 555 Timer 106
Contents vii
6.2.4 Microcontroller Clocks 106
6.3 Frequency Dividers and Counters 107
6.3.1 Frequency Dividers 107
6.3.2 The JK Flip-flop Counter 107
6.3.3 Ripple Counters 108
6.3.4 Decoding Gates 110
6.3.5 Synchronous Counters 110
6.3.6 Counter ICs 112
6.3.7 Shift Registers 113
6.4 Multiplexers and Demultiplexers 115
6.4.1 Multiplexers 115
6.4.2 Demultiplexers 118
6.4.3 Multiplexer and Demultiplexer ICs 118
6.5 Input Devices 118
6.5.1 Switches 118
6.5.2 Switch Contact Bounce 120
6.5.3 Keypads 121
6.6 Output Devices 122
6.6.1 Seven-segment LED 122
6.6.2 Liquid Crystal Displays 124
6.6.3 LCD Technologies 125
Chapter 7 - The Microchip PIC 129
7.0 The PICMicro Microcontroller 129
7.0.1 Programming the PIC 130
PIC Programmers 131
Development Boards 131
7.0.2 Prototyping the PIC Circuit 132
7.1 PIC Architecture 134
7.1.1 Baseline PIC Family 134
PIC10 Devices 135
PIC12 Devices 135
PIC14 Devices 138
7.1.2 Mid-range PIC Family 138
PIC16 Devices 139
7.1.3 High-Performance PIC Family 139
PIC18 Devices 139
Chapter 8 - Mid-range PIC Architecture 141
8.0 Processor Architecture and Design 142
8.0.1 Harvard Architecture 142
8.0.2 RISC CPU Design 143
8.0.3 Single-word Instructions 143
8.0.4 Instruction Format 144
8.0.5 Mid-Range Device Versions 145
8.1 The Mid-range Core Features 145
8.1.1 Oscillator 145
8.1.2 System Reset 147
8.1.3 Interrupts 148
8.2 Mid-Range CPU and Instruction Set 149
viii Microcontroller Programming
8.2.1 Mid-Range Instruction Set 149
8.2.2 STATUS and OPTION Registers 151
8.3 EEPROM Data Storage 153
8.3.1 EEPROM in Mid-Range PICs 153
8.4 Data Memory Organization 154
8.4.1 The w Register 154
8.4.2 The Data Registers 154
Memory Banks 154
The SFRs 155
The GPRs 157
8.4.3 Indirect Addressing 158
8.5 Mid-range I/O and Peripheral Modules 158
8.5.1 I/O Ports 159
8.5.2 Timer Modules 160
8.5.3 Capture-and-Compare Module 160
8.5.4 Master Synchronous Serial Port (MSSP) Module 161
8.5.5 USART Module 161
8.5.6 A/D Module 161
Chapter 9 - PIC Programming: Tools and Techniques 163
9.0 Microchip’s MPLAB 163
9.0.1 Embedded Systems 164
9.1 Integrated Development Environment 165
9.1.1 Installing MPLAB 165
9.1.2 Creating the Project 167
9.1.3 Project Build Options 169
9.1.4 Building the Project 169
9.2 Simulators and Debuggers 170
9.2.1 MPLAB SIM 171
9.2.2 MPLAB Hardware Debuggers 172
9.2.3 A “Quick-and-Dirty” Debugger 174
9.3 Programmers 174
9.4 Engineering PIC Software 175
9.4.1 Using Program Comments 176
Program Header 176
Commented Banners 177
Commented Bitmaps 178
9.4.2 Defining Data Elements 179
The cblock Directive 179
9.4.3 Banking Techniques 180
The banksel Directive 180
Bank Selection Macros 180
Deprecated Banking Instructions 181
9.4.4 Processor and Configuration Controls 182
Configuration Bits 182
9.4.5 Naming Conventions 184
9.4.6 Errorlevel Directive 186
9.5 Pseudo Instructions 186
Contents ix
Chapter 10 - Programming Essentials: Input and Output 189
10.0 16F84A Programming Template 189
10.1 Introducing the 16F84A 191
10.1.1 Template Circuit for 16F84A 191
10.1.2 Power Supplies 191
Voltage Regulator 192
10.1.3 Comparisons in PIC Programming 193
The Infamous PIC Carry Flag 194
10.2 Simple Circuits and Programs 194
10.2.1 A Single LED Circuit 194
LED Flasher Program 196
10.2.2 LED/Pushbutton Circuit 199
10.2.3 Multiple LED Circuit 202
10.3 Programming the Seven-segment LED 204
10.4 A Demonstration Board 206
10.4.1 PCB Images for Demo Board 206
10.4.2 TestDemo1 Program 208
Chapter 11 - Interrupts 211
11.0 Interrupts on the 16F84 211
11.0.1 The Interrupt Control Register 211
11.0.2 The OPTION Register 212
11.1 Interrupt Sources 213
11.1.1 Port-B External Interrupt 214
11.1.2 Timer0 Interrupt 214
11.1.3 Port-B Line Change Interrupt 215
Multiple External Interrupts 217
11.1.4 EEPROM Data Write Interrupt 217
11.2 Interrupt Handlers 217
11.2.1 Context Saving Operations 218
Saving w and STATUS Registers 218
11.3 Interrupt Programming 218
11.3.1 Programming the External Interrupt 219
RB0 Interrupt Initialization 220
RB0 Interrupt Service Routine 221
11.3.2 Wakeup from SLEEP Using the RB0 Interrupt 222
The SleepDemo Program 223
11.3.3 Port-B Bits 4-7 Status Change Interrupt 224
RB4-7 Interrupt Initialization 225
RB4-7 Change Interrupt Service Routine 227
11.4 Sample Programs 229
11.4.1 The RB0Int Program 229
11.4.2 The SleepDemo Program 232
11.4.3 The RB4to7Int Program 235
Chapter 12 - Timers and Counters 241
12.0 The 16F84 Timer0 Module 241
12.0.1 Timer0 Operation 241
x Microcontroller Programming
Timer0 Interrupt 242
Timer0 Prescaler 242
12.1 Delays Using Timer0 243
12.1.1 Long Delay Loops 244
How Accurate the Delay? 245
The Black-Ammerman Method 245
12.2 Timer0 as a Counter 246
12.3 Timer0 Programming 247
12.3.1 Programming a Counter 247
A Timer/Counter Test Circuit 248
The Tmr0Counter Program 248
12.3.2 Timer0 as a Simple Delay Timer 250
12.3.3 Measured Time Lapse 252
Interrupt-driven Timer 255
12.4 The Watchdog Timer 259
12.4.1 Watchdog Timer Programming 260
12.5 Sample Programs 260
12.5.1 The Tmr0Counter program 260
12.5.2 The Timer0 Program 263
12.5.3 The LapseTimer Program 265
12.5.4 The LapseTmrInt Program 269
Chapter 13 - LCD Interfacing and Programming 275
13.0 LCD Features and Architecture 275
13.0.1 LCD Functions and Components 276
Internal Registers 276
Busy Flag 276
Address Counter 276
Display Data RAM (DDRAM) 276
Character Generator ROM (CGROM) 276
Character Generator RAM (CGRAM) 277
Timing Generation Circuit 277
Liquid Crystal Display Driver Circuit 278
Cursor/Blink Control Circuit 278
13.0.2 Connectivity and Pin-Out 278
13.1 Interfacing with the HD44780 279
13.1.1 Busy Flag or Timed Delay Options 280
13.1.2 Contrast Control 281
13.1.3 Display Backlight 281
13.1.4 Display Memory Mapping 281
13.2 HD44780 Instruction Set 283
13.2.1 Instruction Set Overview 283
Clearing the Display 283
Return home 284
Entry mode set 284
Display and Cursor ON/OFF 284
Cursor/display shift 284
Function set 285
Set CGRAM address 285
Set DDRAM address 285
Read busy flag and Address register 285
Contents xi
Write data 285
Read data 286
13.2.2 A 16F84 8-bit Data Mode Circuit 286
13.3 LCD Programming 287
13.3.1 Defining Constants and Variables 287
Using MPLAB Data Directives 289
13.3.2 LCD Initialization 290
Function Set Command 290
Display Off 291
Display and Cursor On 291
Set Entry Mode 292
Cursor and Display Shift 292
Clear Display 293
13.3.3 Auxiliary Operations 293
Time Delay Routine 293
Pulsing the E Line 295
Reading the Busy Flag 295
Bit Merging Operations 296
13.3.4 Text Data Storage and Display 298
Generating and Storing a Text String 299
Displaying the Text String 301
13.3.5 Data Compression Techniques 302
4-bit Data Transfer Mode 302
Master/Slave Systems 304
13.4 Sample Programs 306
13.4.1 LCDTest1 306
13.4.2 LCDTest2 Program 316
13.4.3 LCDTest3 Program 327
Chapter 14 - Communications 339
14.0 PIC Communications Overview 339
14.1 Serial Data Transmission 340
14.1.1 Asynchronous Serial Transmission 340
14.1.2 Synchronous Serial Transmission 342
14.1.3 PIC Serial Communications 342
14.1.4 The RS-232-C Standard 343
Essential Concepts 344
The Serial Bit Stream 344
Parity Testing 345
Connectors and Wiring 345
The Null Modem 346
The Null Modem Cable 347
14.1.5 The EIA-485 Standard 349
EIA-485 in PIC-based Systems 350
14.2 Parallel Data Transmission 350
14.2.1 PIC Parallel Slave Port (PSP) 351
14.3 PIC “Free-style” Serial Programming 351
14.3.1 PIC-to-PIC Serial Communications 352
PIC-to-PIC Serial Communications Circuits 352
PIC-to-PIC Serial Communications Programs 354
14.3.2 Program Using Shift Register ICs 360
xii Microcontroller Programming
The 74HC165 Parallel-to-Serial Shift Register 361
74HC164 Serial-to-Parallel Shift Register 364
14.4 PIC Protocol-based Serial Programming 366
14.4.1 RS-232-C Communications on the 16F84 366
The RS-232-C Transceiver IC 367
PIC to PC Communications 368
An RS-232-C TTY Board 368
A 16F84A UART Emulation 369
An LCD Scrolling Routine 371
14.4.2 RS-232-C Communications on the 16F87x 375
The 16F87x USART Module 376
The USART Baud Rate Generator 376
16F87x USART Asynchronous Transmitter 379
16F87x USART Asynchronous Receiver 380
PIC-to-PC RS-232-C Communications Circuit 381
16F877 PIC Initialization Code 381
USART Receive and Transmit Routines 384
The USART Receive Interrupt 386
14.5 Sample Programs 389
14.5.1 SerialSnd Program 389
14.5.2 SerialRcv Program 394
14.5.3 Serial6465 Program 400
14.5.4 TTYUsart Program 404
14.5.5 SerComLCD Program 420
14.5.6 SerIntLCD Program 438
Chapter 15 - Data EEPROM Programming 459
15.0 PIC Internal EEPROM Memory 460
15.0.1 EEPROM Programming on the 16F84 460
Reading EEPROM Data Memory on the 16F84 460
16F84 EEPROM Data Memory Write 461
16F84 EEPROM Demonstration Program 462
15.0.2 EEPROM Programming on the 16F87x 465
Reading EEPROM Data Memory on the 16F87x 467
Writing to EEPROM Data Memory in the 16F87x 467
GFR Access Issue in the 16F87x 469
15.0.3 16F87x EEPROM Circuit and Program 469
15.1 EEPROM Devices and Interfaces 475
15.1.1 The I2C Serial Interface 476
15.1.2 I2C Communications 476
15.1.3 EEPROM Communications Conditions 477
15.1.4 EEPROM Write Operation 478
15.1.5 EEPROM Read Operation 478
15.1.6 I2C EEPROM Devices 479
15.1.7 PIC Master Synchronous Serial Port (MSSP) 480
MSSP in Master Mode 482
15.1.8 I2C Serial EEPROM Programming on the 16F877 486
IC2 Initialization Procedure 486
I2C Write Byte Procedure 488
I2C Read Byte Procedure 490
15.2 Sample Programs 492
Contents xiii
15.2.1 EECounter Program 492
15.2.2 Ser2EEP Program 504
15.2.3 I2CEEP Program 521
Chapter 16 - Analog to Digital and Realtime Clocks 543
16.0 A/D Converters 544
16.0.1 Converter Resolution 544
16.0.2 ADC Implementation 545
16.1 A/D Integrated Circuits 546
16.1.1 ADC0331 Sample Circuit and Program 547
16.2 PIC On-Board A/D Hardware 549
16.2.1 A/D Module on the 16F87x 549
The ADCON0 Register 550
The ADCON1 Register 552
SLEEP Mode Operation 554
16.2.2 A/D Module Sample Circuit and Program 554
16.3 Realtime Clocks 558
16.3.1 The NJU6355 Realtime Clock 558
16.3.2 RTC Demonstration Circuit and Program 560
BCD Conversion Procedures 565
16.4 Sample Programs 568
16.4.1 ADF84 Program 568
16.4.2 A2DinLCD Program 580
16.4.3 RTC2LCD Program 595
Appendix A - Resistor Color Codes 613
Appendix B - Building Your Own Circuit Boards 615
Appendix C - Mid-range Instruction Set 621
Appendix D - Supplementary Programs 659
Index 795